Metal-oxide-semiconductor (MOS) is a dominating technology for integrated circuits at 90 nm technology and beyond. A MOS device can work in three regions, depending on gate voltage Vg and source-drain voltage Vds, linear, saturation, and sub-threshold regions. The sub-threshold region is a region where Vg is smaller than the threshold voltage Vt. A parameter known as sub-threshold swing (SS) represents the easiness of switching the transistor current off and thus is an important factor in determining the speed of a MOS device. The sub-threshold swing can be expressed as a function of m*kT/q, where m is a parameter related to capacitance. The sub-threshold swing of a typical MOS device has a limit of about 60 mV/decade (kT/q) at room temperature, which in turn sets a limit for further scaling of operation voltage VDD and threshold voltage Vt. This limitation is due to the diffusion transport mechanism of carriers. For this reason, existing MOS devices typically cannot switch faster than 60 mV/decade at room temperatures. The 60 mV/decade sub-threshold swing limit also applies to FinFET or ultra thin-body MOSFET on silicon-on-insulator (SOI) devices. However, even with better gate control over the channel, an ultra thin body MOSFET on SOI or FinFET can only achieve close to, but not below, the limit of 60 mV/decade. With such a limit, faster switching at low operation voltages for future nanometer devices cannot be achieved.
To solve the above-discussed problem, tunnel field-effect transistors (FET) have been explored. Tunnel Field Effect Transistors (TFET's) can improve both of these parameters by changing the carrier injection mechanism. In a conventional MOSFET, the SS is limited by the diffusion of carriers over the source-to-channel barrier where the injection current is proportional to kT/q. Hence at room temperature, the SS is 60 mV/dec. In a TFET, injection is governed by the band-to-band tunneling from the valence of the source to the conduction band of the channel. Accordingly, much lower SS can be achieved. Since the tunnel FET is designed on a p-i-n diode configuration, much lower leakage currents are achieved. Also, the device is more resistant to short-channel effects seen in conventional MOSFETs.
In TFETs, the source and drain region are doped asymmetrically. Also, to achieve better TFET performance, sharp junctions are required which is difficult to achieve by implanted junctions. These issues limited most of the TFET fabrication attempts to vertical growth of the source channel and drain. The resulting TFETs suffered from high overlap capacitances between the gates and source/drain regions, and hence the transistor gate delays are increased. Attempts to fabricate horizontal TFET's typically involve complex schemes (since source and drain need to be separately implanted) that limit the scalability of such devices. Another issue arising from heavily doped source/drain regions is ambi-polarity in tunnel FETs due to asymmetrically doped source/drain and device working principle. Therefore there is need for device design to suppress ambi-polarity.